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MOSEL VITELIC
V58C265164S 64 Mbit DDR SDRAM 2.5 VOLT 4M X 16
PRELIMINARY
4 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Cycle Time (tCK2.5) Clock Cycle Time (tCK2) 250 MHz 4 ns 4.8 ns 6 ns
45 225 MHz 4.5 ns 5.4 ns 6.75 ns
5 200 MHz 5 ns 6 ns 7.5 ns
55 183 MHz 5.5 ns 6.6 ns 8.25 ns
Features
I 4 banks x 1Mbit x 16 organization I High speed data transfer rates with system frequency up to 250 MHz I Data Mask for Write Control (DM) I Four Banks controlled by BA0 & BA1 I Programmable CAS Latency: 2, 2.5, 3 I Programmable Wrap Sequence: Sequential or Interleave I Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type I Automatic and Controlled Precharge Command I Suspend Mode and Power Down Mode I Auto Refresh and Self Refresh I Refresh Interval: 4096 cycles/64 ms I Available in 66-pin 400 mil TSOP-II I SSTL-2 Compatible I/Os I Double Data Rate (DDR) I Bidirectional Data Strobe (DQs) for input and output data, active on both edges I On-Chip DLL aligns DQ and DQs transitions with CLK transitions I Differential clock inputs CLK and CLK I Power supply 2.5V 0.2V
Description
The V58C265164S is a four bank DDR DRAM organized as 4 banks x 1Mbit x 16. The V58C265164S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating Temperature Range
0C to 70C
Package Outline JEDEC 66 TSOP II
*
CLK Cycle Time (ns) -4
*
Power -55
*
-45
*
-5
*
Std.
*
L
*
Temperature Mark
Blank
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66 Pin Plastic TSOP-II PIN CONFIGURATION Top View
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CLK CLK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
V58C265164S
Pin Names
CLK, CLK CKE CS RAS CAS WE UDQS, LDQS A0-A11 BA0, BA1 DQ0-DQ15 UDM, LDM VDD VSS VDDQ VSSQ NC VREF Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe (Bidirectional) Address Inputs Bank Select Data Input/Output Data Mask Power (+2.5V) Ground Power for I/O's (+2.5V) Ground for I/O's Not connected Reference Voltage for Inputs
64M DDR SDRAM
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Capacitance*
TA = 0 to 70C, VCC = 2.5 V 0.2 V, f = 1 Mhz
Symbol Parameter CI1 CI2 CIO CCLK Input Capacitance (A0 to A11) Input Capacitance RAS, CAS, WE, CS, CKE Output Capacitance (DQ) Input Capacitance (CCLK, CLK)
V58C265164S
Absolute Maximum Ratings*
Max. Unit
5 5 pF pF
Operating temperature range .................. 0 to 70 C Storage temperature range ................-55 to 150 C Input/output voltage.................. -0.3 to (VCC+0.3) V Power supply voltage .......................... -0.3 to 4.6 V Power dissipation ...........................................1.6 W Data out current (short circuit).......................50 mA
*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6.5 4
pF pF
*Note: Capacitance is sampled and not 100% tested.
Block Diagram
Column Addresses A0 - A7, AP, BA0, BA1 Row Addresses A0 - A11, BA0, BA1
Column address counter
Column address buffer
Row address buffer
Refresh Counter
Row decoder Memory array
Column decoder Sense amplifier & I(O) bus
Row decoder Memory array
Column decoder Sense amplifier & I(O) bus
Row decoder Memory array Bank 2
Row decoder Memory array Bank 3
Bank 0
Bank 1
4096 x 256 x 16 bit
4096 x 256 x 16 bit
Column decoder Sense amplifier & I(O) bus
4096 x 256 x 16 bit
Column decoder Sense amplifier & I(O) bus
4096 x 256 x 16 bit
Input buffer
Output buffer
Control logic & timing generator
I/Q0-IQ15 CKE RAS CAS WE CS CLK, CLK DLL Strobe Gen. Data Strobe UDM LDM CLK CLK
DQS
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Signal Pin Description
Pin
CLK CLK CKE
V58C265164S
Type
Input
Signal
Pulse
Polarity
Positive Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising edge of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. Active High Active on both edges for data input and output. Center aligned to input data Edge aligned to output data -- During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: 8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits) In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS WE DQS
Input
Pulse
Input/ Output
Pulse
A0 - A11
Input
Level
BA0, BA1 DQx
Input
Level
--
Selects which bank is to be active.
Input/ Output Input
Level
--
Data Input/Output pins operate in the same manner as on conventional DRAMs.
DM
Pulse
Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high. Power and ground for the input buffers and the core logic.
VDD, VSS Supply VDDQ VSSQ VREF Supply -- --
Isolated power supply and ground for the output buffers to provide improved noise immunity. SSTL Reference Voltage for Inputs
Input
Level
--
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Functional Description
V58C265164S
I Power-Up Sequence The following sequence is required for POWER UP. 1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.) - Apply VDD before or at the same time as VDDQ. - Apply VDDQ before or at the same time as VTT & Vref. 2. Start clock and maintain stable condition for a minimum of 200us. 3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high. 4. Precharge all banks. 5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0 and "Low" to all of the rest address pins, A1~A11 and BA1) 6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is required to lock the DLL. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0) 7. Issue precharge commands for all banks of the device. 8. Issue 2 or more auto-refresh commands. 9. Issue a mode register set command to initialize device operation.
Note1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it, the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.
Power up Sequence & Auto Refresh(CBR)
0 CK, CK
** **
2 Clock min. 2 Clock min.
EMRS MRS DLL Reset precharge ALL Banks
1
2
3
4
5
6
7
8
9
10
**
11
12
13
14
**
15
16
17
18
19
tRP
1st Auto Refresh
tRFC
** **
2nd Auto Refresh
tRFC
** **
2 Clock min.
Mode Register Set Any Command
Command
200 S Power up to 1st command
precharge ALL Banks
min. 200 Cycle
4
5
6
7
8
8
Extended Mode Register Set (EMRS)
The extended mode register stores the data for enabling or disabling DLL. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. A1 is used at EMRS to indicate I/O strength A1 = 0 full strength, A1 = 1 half strength. Refer to the table for specific codes.
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Mode Register Set (MRS)
V58C265164S
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0 (The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock cycles are required to meet tMRD spec. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency (read latency from column address) uses A4 ~ A6. A7 is a Mosel Vitelic specific test mode during production test. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. 1. MRS can be issued only at all banks precharge state. 2. Minimum tRP is required to issue MRS command.
Address Bus
BA1
BA 0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0 0
MRS MRS RFU DLL
RFU : Must be set "0" TM CAS Latency BT
I/O
DLL
Extended Mode Register Mode Register
Burst Length
A8 0 1 BA0 0 1 An ~ A0
DLL Reset No Yes
A7 0 1
mode Normal Test A4 0 1 0 1 0 1 0 1 Latency Reserve Reserve 2 3 Reserve Reserve 2.5 Reserve
A3 0 1
Burst Type Sequential Interleave Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
A1 0 1
I/O Strength Full Half Latency
A0 0 1
DLL Enable Enable Disable
CAS Latency A6 A5 0 0 0 0 1 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 0 0 1 1 0 0 1 1 (Existing)MRS Cycle Extended Funtions(EMRS)
Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve
Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve
Mode Register Set
0 CK, CK Command
tCK
1
2
3
*1 Mode Register Set
4
5
6
7
8
Precharge All Banks
Any Command
tRP
*2
tMRD
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Mode Register Set Timing
T0 T1 tCK CK, CK Command
Pre- All MRS/EMRS ANY
V58C265164S
T2
T3 tRP
T4
T5 tMRD
T6
T7
T8
T9
Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state. If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command to allow time for the DLL to lock onto the clock.
Burst Mode Operation
Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and burst length. These parameters are programmable and are determined by address bits A0--A3 during the Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length and Sequence table below for programming information.
Burst Length and Sequence
Burst Length
2 xx1 x00 x01 4 x10 x11 000 001 010 011 8 100 101 110 111 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5, 6 7, 0, 1, 2, 3, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 2, 3, 0, 1 3, 0, 1, 2 0,1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 2, 3, 0, 1 3, 2, 1, 0 0,1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 1, 0 0, 1, 2, 3 1, 2, 3, 0 1, 0 0, 1, 2, 3 1, 0, 3, 2
Starting Length (A2, A1, A0)
xx0
Sequential Mode
0, 1
Interleave Mode
0, 1
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Bank Activate Command
V58C265164S
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0 and BA1) are supported. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from the Bank Activate command to the first Read or Write command must meet or exceed the minimum RAS to CAS delay time (tRCD min). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD min).
Bank Activation Timing
(CAS Latency = 2; Burst Length = Any) T0 T1 T2 tRAS(min) tRCD(min) CK, CK BA/Address Command
Bank/Row Activate/A Bank/Col Read/A Bank Pre/A Bank/Row Activate/A Bank/Row Activate/B
T3
Tn tRC
Tn+1
Tn+2 tRP(min)
Tn+3
Tn+4 tRRD(min)
Tn+5
Begin Precharge Bank A
Read Operation
With the DLL enabled, all devices operating at the same frequency within a system are ensured to have the same timing relationship between DQ and DQS relative to the CK input regardless of device density, process variation, or technology generation. The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock frequency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and the system clock (CK) are all nominally aligned. Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed and used to latch the output data into the receiving device. The tolerance for skew between DQS and DQ (tDQSQ) is tighter than that possible for CK to DQ (tAC) or DQS to CK (tDQSCK).
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V58C265164S
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK) During Read Cycles
(CAS Latency = 2.5; Burst Length = 4) T0 T1 T2 T3 T4
CK, CK
Command
READ
NOP
NOP
NOP
NOP tDQSCK(max) tDQSCK(min)
DQS tAC(min) tAC(max)
DQ
D0
D1
D2
D3
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a memory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to the output data. The minimum data output valid time (tDV) and minimum data strobe valid time (tDQSV) are derived from the minimum clock high/low time minus a margin for variation in data access and hold time due to DLL jitter and power supply noise.
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V58C265164S
Output Data and Data Strobe Valid Window for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2) T0 T1 T2 T3 T4
CK, CK
Command
READ
NOP
NOP
NOP
DQS
tDQSV(min)
DQ
D0
D1
tDV(min)
Read Preamble and Postamble Operation
Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe "read preamble" (tRPRE). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of valid data. Once the burst of read data is concluded and given that no subsequent burst read operations are initiated, the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data strobe "read postamble" (tRPST). This transition happens nominally one-half clock period after the last edge of valid data. Consecutive or "gapless" burst read operations are possible from the same DDR SDRAM device with no requirement for a data strobe "read" preamble or postamble in between the groups of burst data. The data strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cycles.
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V58C265164S
Data Strobe Preamble and Postamble Timings for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2) T0 T1 T2 T3 T4
CK, CK
Command
READ
NOP
NOP tRPRE(max)
NOP
tRPRE(min) DQS tDQSQ(min)
tRPST(min)
tRPST(max)
DQ
D0
D1 tDQSQ(max)
Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK Command DQS DQ D0A D1A D2A D3A D0B D1B D2B D3B ReadA NOP ReadB NOP NOP NOP NOP NOP NOP
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK Command DQS DQ D0A D1A D2A D3A D0B D1B D2B D3B ReadA NOP NOP ReadB NOP NOP NOP NOP NOP
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Auto Precharge Operation
V58C265164S
The Auto Precharge operation can be issued by having column address A10 high when a Read or Write command is issued. If A10 is low when a Read or Write command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. When the Auto Precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the Read or Write cycle once tRAS(min) is satisfied. Read with Auto Precharge If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency programmed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (tRP) has been satisfied.
Read with Autoprecharge Timing
(CAS Latency = 2; Burst Length = 4) T0 T1 T2 T3 tRAS(min) CK, CK Command DQS DQ D0 D1 D2 D3 BA NOP R w/AP NOP NOP NOP NOP NOP BA T4 T5 T6 T7 tRP(min) T8 T9
Begin Autoprecharge Earliest Bank A reactivate
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V58C265164S
Read with Autoprecharge Timing as a Function of CAS Latency
(CAS Latency = 2, 2.5, 3; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRP(min) T7 T8 T9
tRAS(min) CK, CK Command BA NOP NOP RAP NOP NOP
NOP
BA
NOP
NOP
DQS DQ D0 D1 D2 D3
CAS Latency=2 DQS DQ D0 D1 D2 D3
CAS Latency=2.5 DQS DQ D0 D1 D2 D3
CAS Latency=3
Begin Autoprecharge
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V58C265164S
Precharge Timing During Read Operation For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time (tRP). A Precharge command can not be issued until tRAS(min) is satisfied.
Read with Precharge Timing as a Function of CAS Latency
(CAS Latency = 2, 2.5, 3; Burst Length = 4) T0 T1 T2 T3 T4 T5 T6 tRP(min) T7 T8 T9
tRAS(min) CK, CK Command BA NOP NOP Read NOP PreA
NOP
BA
NOP
NOP
DQS DQ D0 D1 D2 D3
CAS Latency=2 DQS DQ D0 D1 D2 D3
CAS Latency=2.5 DQS DQ D0 D1 D2 D3
CAS Latency=3
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Burst Stop Command
V58C265164S
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay (LBST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a burst Write cycle, the command will be treated as a NOP command.
Read Terminated by Burst Stop Command Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 4) T0 CK, CK Command Read LBST DQS CAS Latency = 2 DQ LBST DQS CAS Latency = 2.5 DQ LBST DQS CAS Latency = 3 DQ D0 D1 D0 D1 D0 D1 BST NOP NOP NOP NOP T1 T2 T3 T4 T5 T6
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V58C265164S
Read Interrupted by a Precharge A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to Output Disable latency is equivalent to the CAS latency.
Read Interrupted by a Precharge Timing
(CAS Latency = 2, 2.5, 3; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 tRP(min) T7 T8 T9
tRAS(min) CK, CK Command BA NOP NOP Read NOP PreA
NOP
BA
NOP
NOP
DQS DQ D0 D1 D2 D3
CAS Latency=2 DQS DQ D0 D1 D2 D3
CAS Latency=2.5 DQS DQ D0 D1 D2 D3
CAS Latency=3
Burst Write Operation
The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. The memory controller is required to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be driven high nominally one clock after the write command has been registered. Timing parameters tDQSS(min) and tDQSS(max) define the allowable window when the data strobe must be driven high. Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is registered into the device (WL=1). The input data valid window is nominally centered around the midpoint of the data strobe signal. The data window is defined by DQ to DQS setup time (tQDQSS) and DQ to DQS hold time (tQDQSH). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Write Preamble and Postamble Operation Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe "write preamble". This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write command has been registered by the device. The preamble is explicitly defined by a setup time (tWPRES(min)) and hold time (tWPREH(min)) referenced to the first falling edge of CK after the write command.
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Burst Write Timing
V58C265164S
(CAS Latency = Any; Burst Length = 4) T0 T1 T2 T3 T4
CK, CK
Command
WRITE tWPREH tWPRES
NOP
NOP
NOP
tWPST tQDQSS
DQS(nom)
tDQSS tQDQSH tQDQSS
tQDQSH
DQ(nom)
D0
D1
D2
D3
tWPREH(min) tWPRES(min) DQS(min) tDQSS(min)
DQ(min)
D0
D1
D2
D3
tWPRES(max) tWPREH(max) DQS(max)
tDQSS(max) DQ(max) D0 D1 D2 D3
Once the burst of write data is concluded and given that no subsequent burst write operations are initiated, the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data strobe "write postamble". This transition happens nominally one-half clock period after the last data of the burst cycle is latched into the device.
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MOSEL VITELIC
V58C265164S
Write Interrupted by a Precharge A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only restriction being that the interval that separates the commands be at least one clock cycle.
Write Interrupted by a Precharge Timing
(CAS Latency = 2; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
CK, CK Command DQS DQ DM D0 D1 D2 D3 D4 D5
WriteA
NOP
NOP
PreA NOP tWR
NOP
NOP
NOP
NOP
NOP
NOP
Data is masked by DM input
Data is masked by Precharge Command DQS input ignored
Write with Auto Precharge If A10 is high when a Write command is issued, the Write with auto Precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWR (min.).
Write with Auto Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8 tRP(min)
T9
T10
tRAS(min) CK, CK Command BA NOP NOP WAP NOP NOP NOP NOP
NOP
NOP
BA
tWR(min) DQS DQ D0 D1 D2 D3
Begin Autoprecharge
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
Precharge Timing During Write Operation
V58C265164S
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery requirement. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The "write recovery" operation begins on the rising clock edge after the last DQS edge that is used to strobe in the last valid write data. "Write recovery" is complete on the next rising clock edge that is used to strobe in the Precharge command. For the earliest possible Precharge command following a Write burst without interrupting the burst, the minimum time for "write recovery" is 1.25 clock cycles. Maximum "write recovery" time is 1.75 clock cycles.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8 tRP(min)
T9
T10
tRAS(min) CK, CK Command BA NOP NOP Write NOP NOP NOP PreA
NOP
NOP
BA
tWR(min) DQS DQ D0 D1 D2 D3 tWR(max) DQS DQ D0 D1 D2 D3
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
Data Mask Function
V58C265164S
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask to Data Latency = 0). When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
(CAS Latency = Any; Burst Length = 8) T0 CK, CK Command Write tDMDQSS DQS tDMDQSH DQ D0 D1 D2 D3 D4 D5 D6 D7 tDMDQSH NOP NOP NOP NOP NOP tDMDQSS NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
DM
Burst Interruption
Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting Read command appears on the bus. Read commands can be issued on each rising edge of the system clock. It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = 2; Burst Length = 4) T0 CK, CK Command DQS DQ DA0 DA1 DB0 DB1 DB2 DB3 ReadA ReadB NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
V58C265164S
Read Interrupted by a Write To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or latency (LBST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half clock cycles, the minimum delay (LBST) is rounded up to the next full clock cycle (i.e., if CL=2 then LBST=2, if CL=2.5 then LBST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.
Read Interrupted by Burst Stop Command Followed by a Write Command Timing
(CAS Latency = 2; Burst Length = 4) T0 CK, CK Command DQS DQ D0 LBST D1 D0 D1 D2 D3 Read BST NOP Write NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
Write Interrupted by a Write A Burst Write can be interrupted before completion by a new Write command to any bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. The data from the first Write command continues to be input into the device until the Write Latency of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write command is input into the device. Write commands can be issued on each rising edge of the system clock. It is illegal to interrupt a Write with autoprecharge command with a Write command.
Write Interrupted by a Write Command Timing
(CAS Latency = Any; Burst Length = 4) T0 CK, CK Command DQS DQ DM DA0 DA1 DB0 DB1 DB2 DB3 DM0 DM1 DM0 DM1 DM2 DM3 Write Latency WriteA WriteB NOP NOP NOP NOP NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9
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MOSEL VITELIC
V58C265164S
Write Interrupted by a Read A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory array. Any data that is present on the DQ pins coincident with or following the Read command will be masked off by the Read command and will not be written to the array. The memory controller must give up control of both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in order to avoid contention. In order to avoid data contention within the device, a delay is required (tCDLR) from the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write with autoprecharge command with a Read command.
Write Interrupted by a Read Command Timing
(CAS Latency = 2; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
CK, CK Command DQS DQ DM D0 D1 D2 D3 D4 D5 D0 D1 D2 D3 D4 D5 D 6 D7 Write NOP NOP tCDLR Read NOP NOP NOP NOP NOP NOP NOP
Data is masked by DM input
Data is masked by Read command DQS input ignored
Auto Refresh
The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the rising edge of the clock. All banks must be precharged and idle for a tRP(min) before the Auto Refresh command is applied. No control of the address pins is required once this cycle has started because of the internal address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and the next Activate command or subsequent Auto Refresh command must be greater than or equal to the tRFC(min). Commands may not be issued to the device once an Auto Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be registered on each rising edge of the CK input until the refresh period is satisfied.
Auto Refresh Timing
T0 T1 T2 tRP T3 T4 T5 T6 T7 tRFC T8 T9 T10 T11
CK, CK Command
Pre All Auto Ref
NOP
ANY
CKE
High
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MOSEL VITELIC
Self Refresh
V58C265164S
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE high for longer than tSREX for locking of DLL. The auto refresh is required before self refresh entry and after self refresh exit.
CK, CK Command CKE
Self Refresh
** ** **
Stable Clock NOP
** ** **
Auto Refresh
** tSREX
Power Down Mode
The power down mode is entered when CKE is low and exited when CKE is high. Once the power down mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce power consumption. All banks should be in idle state prior to entering the precharge power down mode and CKE should be set high at least 1tck+tIS prior to row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period (tREF) of the device.
CK, CK
**
**
Command
Precharge
Precharge power down Entry
precharge
**
power down Exit
Active
**
NOP
Read
CKE
**
**
Active power down Entry
Active power down Exit
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
SSTL_2 Input AC/DC Logic Levels
Symbol
VIH (DC) VIH (AC) VIL (DC) VIL (AC)
V58C265164S
Parameter
DC Input Logic High AC Input Logic High DC Input Logic Low AC Input Logic Low
Min
VREF+0.18 VREF+0.35 -0.30 --
Max VDDQ+0.3 -- VREF-0.18 VREF-0.35
Units
V V V V
Notes
1
Note: 1. The relationship of the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that supports SSTL_2 inputs but has no SSTL_2 outputs (e.g., a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0V (High corner VDDQ+300mV.)
SSTL_2 AC Test Conditions
Symbol
VREF VSWING (max) SLEW
Parameter
Input Reference Voltage Input Signal Maximum Peak to Peak Swing Input Signal Minimum Slew Rate
Value
0.5*VDDQ 1.5 1.0
Units
V V V/ns
Notes
1 1, 2 3
Notes: 1. Input waveform timing is referenced to the input signal crossing the VREF level applied to the device. 2. Compliant devices must still meet the VIH (AC) and VIL (AC) specifications under actual use conditions. 3. The 1 V/ns input signal minimum slew rate is to be maintained in the VIL max (AC) to VIL min (AC) range of the input signal swing.
SSTL_2 Output Buffers
I I I I The input voltage provided to the receiver depends on three parameters: VDDQ and current drive capabilities of the output buffer Termination voltage Termination resistance VDDQ VDD
Class II SSTL_2 Output Buffer (Driver)
VDDQ VTT = 0.5 *VDDQ RT=50 Output Buffer VREF VOUT VSSQ VIN CLOAD = 30pF
Receiver
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MOSEL VITELIC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70C
Parameter
Operating Current (One Bank Active) Precharge Standby Current in Power-Down Mode Precharge Standby Current in Non Power-Down Mode Active Standby Current in Power-Down Mode
V58C265164S
Symbol
ICC1 ICC2P ICC2N ICC3P
Test Condition
CAS Latency
Version -4
150
-45
145
-5
140
-55
135
Unit
mA
Burst Length=2 tRC=tRC(min) IOL=0mA CKE=VIL(max), tCC=10ns CKE=VIH(min), CS-VIH(min), tCC=10ns Input signals are changed once during 20ns CKE=VIL(max), tCC=10ns CKE=VIH(min), CS-VIH(min), tCC=10ns Input signals are changed once during 20ns IOL=0mA Page Burst All Banks activated tCCD=2CKs tRC=tRFC (min) CKE=0.2V 2
20
mA
45
mA
30
mA
Active Standby Current in Non- ICC3N Power-Down Mode
60
mA
160
155
150
145
mA
Operating Current (Burst Mode) ICC4
Refresh Current Self Refresh Current
ICC5 ICC6
200 2
mA mA
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MOSEL VITELIC
V58C265164S
AC Characteristics (TA=0 to +70C, VCC=2.5 0.2V)
-4 Symbol Clock Cycle
tCK Clock Cycle CL = 2.0 CL = 2.5 CL = 3.0 tCH tCL Clock Duty Cycle 6 4.8 4 0.45 0.45 15 15 15 0.55 0.55 6.75 5.4 4.5 0.45 0.45 15 15 15 0.55 0.55 7.5 6 5 0.45 0.45 15 15 15 0.55 0.55 8.25 6.6 5.5 0.45 0.45 15 15 15 0.55 0.55 ns ns ns % %
-45 Max. Min. Max. Min.
-5 Max.
-55 Min. Max. Unit
Parameter
Min.
Command Cycle
tRAS tRP tRC tRCD tRRD tRFC tREF tSREX(DLL) tSREX tIS tIH tCCD tMRD tPDENT tPDEX(DLL) tPDEX CMD, ADDR->CLK Setup CMD, ADDR->CLK Hold CAS->CAS Delay (Cola->Colb) Mode Register Set Delay Power Down Entry Delay Power Down Exit Delay Row Active Time (ACT->PRE) Row Precharge (PRE->ACT) Row Cycle (ACT->ACT) RAS->CAS Delay (ACT->WR/RD) RAS->RAS Delay (ACTa->ACTb) Auto-Refresh (REF->REF/ACT) Refresh Cycle Self-Refresh Exit Delay 40 18 60 18 8 68 200 1 0.9 0.9 1 2 1 1 1 100K 64 40 18 60 18 9 68 200 1 0.9 0.9 1 2 1 1 1 100K 64 40 18 60 20 10 70 200 1 1.0 1.0 1 2 1 1 1 100K 64 40 20 60 20 12 70 200 1 1.8 1.8 1 2 1 1 1 100K 64 ns ns ns ns ns ns ms cycles tRC ns ns tCK tCK tCK tCK tCK
Read Cycle
tAC tDQSCK tDQSQ tDV tRPRE tRPST CLK->DQ Skew CLK->DQS Skew DQS->DQ Skew DQ/DQS Valid Window Read DQS Preamble Read DQS Postamble -0.1 -0.1 -0.075 0.3 0.9 0.4 0.1 0.1 0.075 1.1 0.6 -0.1 -0.1 -0.075 0.3 0.9 0.4 0.1 0.1 0.075 1.1 0.6 -0.1 -0.1 -0.075 0.3 0.9 0.4 0.1 0.1 0.075 1.1 0.6 -0.1 -0.1 -0.075 0.3 0.9 0.4 0.1 0.1 0.075 1.1 0.6 tCK tCK tCK tCK tCK tCK
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
AC Characteristics (Continued) (TA=0 to +70C, VCC=2.5 0.2V)
-4 Symbol Write Cycle
tWPRES tWPREH tDQSS tDSH tDSL tWPST tDQSR tWR tDS tDH tQDQSS tQDQSH tDMDSQS tDMDQSH Write Preamble DQS Setup Write Preamble DQS Hold Write Preamble CLK->DQS (first) Write DQS High Width Write DQS Low Width Write Postamble DQS (last) -> Hi-Z Write (last DIN) -> READ Command Write (last DIN) -> PRE Command DQ/DM -> DQS Setup (Data Setup) DQ/DM -> DQS Hold (Data Hold) Date Input to Data Strobe Setup Time Date Input to Data Strobe Hold Time Date Mask to Data Strobe Setup Time Date Mask to Data Strobe Hold Time 0 0.25 0.75 0.4 0.4 0.4 1.25 1.25 0.075 0.075 0.075 0.075 0.075 0.075 0.5 1.25 1.25 0.6 0.6 0.6 1.75 1.75 0 0.25 0.75 0.4 0.4 0.4 1.25 1.25 0.075 0.075 0.075 0.075 0.075 0.075 0.5 1.25 1.25 0.6 0.6 0.6 1.75 1.75 0 0.25 0.75 0.4 0.4 0.4 1.25 1.25 0.075 0.075 0.075 0.075 0.075 0.075 0.5 1.25 1.25 0.6 0.6 0.6 1.75 1.75 -
V58C265164S
-45 Max. Min. Max. Min.
-5 Max.
-55 Min. Max. Unit
Parameter
Min.
0 0.25 0.75 0.4 0.4 0.4 1.25 1.25 0.075 0.075 0.075 0.075 0.075 0.075
0.5 1.25 1.25 0.6 0.6 0.6 1.75 1.75 -
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
Complete List of Operation Commands DDR SDRAM Function Truth Table
CURRENT STATE1
Idle
V58C265164S
CS
H L L L L L L L H L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L
RAS
X H H H L L L L X H H H L L L X H H H H L L L X H H H H L L L X H H H H L L L
CAS
X H H L H H L L X H L L H H L X H H L L H H L X H H L L H H L X H H L L H H L
WE
X H L X H L H L X X H L H L X X H L H L H L X X H L H L H L X X H L H L H L X
BS
X X BS BS BS BS X OpX X BS BS BS BS X X X BS BS BS BS BS X X X BS BS BS BS BS X X X BS BS X BS BS X
Addr
X X X X RA AP X Code X X CA,AP CA,AP X AP X X X X CA,AP CA,AP X AP X X X X CA,AP CA,AP X AP X X X X X X X AP X
ACTION
NOP or Power Down NOP ILLEGAL2 ILLEGAL2 Row (&Bank) Active; Latch Row Address NOP4 Auto-Refresh or Self-Refresh5 Mode reg. Access5 NOP NOP Begin Read; Latch CA; DetermineAP Begin Write; Latch CA; DetermineAP ILLEGAL2 Precharge ILLEGAL NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Term Burst Term Burst, New Read, DetermineAP3 ILLEGAL (Need Term Burst before Write) ILLEGAL to Same Bank, other Bank 0K if tRRD is Satisfied Term Burst, Precharge ILLEGAL NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) NOP Term Burst, Start Read, DetermineAP3 Term Burst, New Write, DetermineAP3 ILLEGAL2 Term Burst, Precharge3 ILLEGAL NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL
Row Active
Read
Write
Read with Auto Precharge
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
DDR SDRAM Function Truth Table (continued)
CURRENT STATE1
Write with Auto Precharge
V58C265164S
CS
H L L L L L L L H L L L L L L H L L L L L L H L L L L L L H L L L L H L L L L
RAS
X H H H H L L L X H H H L L L X H H H L L L X H H H L L L X H H L L X H H H L
CAS
X H H L L H H L X H H L H H L X H H L H H L X H H L H H L X H L H L X H H L X
WE
X H L H L H L X X H L X H L X X H L X H L X X H L X H L X X X X X X X H L X X
BS
X X BS BS X BS BS X X X BS BS BS BS X X X BS BS BS BS X X X BS BS BS BS X X X X X X X X X X X
Addr
X X X X X X AP X X X X X X AP X X X X X X AP X X X X X X AP X X X X X X X X X X X
ACTION
NOP (Continue Burst to End;> Precharge) NOP (Continue Burst to End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after tRP NOP;> Idle after tRP NOP ILLEGAL2 (0K Provided tRP Satisfied) ACT NOP4 ILLEGAL NOP;> Row Active after tRCD NOP;> Row Active after tRCD ILLEGAL2 (0K if tRCD satisfied) Read/Write (0K to other Bank if tRRD Satisfied) ACT Precharge ILLEGAL NOP NOP ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after tRC NOP;> Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL ILLEGAL ILLEGAL
Precharging
Row Activating
Write Recovering
Refreshing
Mode Register Accessing
V58C265164S Rev. 1.7 August 2001
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MOSEL VITELIC
Clock Enable (CKE) Truth Table
STATE(n)
Self-Refresh6
V58C265164S
CKE n-1
H L L L L L L H L L L L L L H H H H H H H H L H H L L
CKE n
X H H H H H L X H H H H H L H L L L L L L L L H L H L
CS
X H L L L L X X H L L L L X X H L L L L L L X X X X X
RAS
X X H H H L X X X H H H L X X X H H H L L L X X X X X
CAS
X X H H L X X X X H H L X X X X H H L H L L X X X X X
WE
X X H L X X X X X H L X X X X X H L X X H L X X X X X
Addr
X X X X X X X X X X X X X X X X X X X X X X X X X X X
ACTION
INVALID EXIT Self-Refresh, Idle after tRC EXIT Self-Refresh, Idle after tRC ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID EXIT Power-Down, > Idle. EXIT Power-Down, > Idle. ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Low-Power Mode) Refer to the function truth table Enter Power- Down Enter Power- Down ILLEGAL ILLEGAL ILLEGAL Enter Self-Refresh ILLEGAL NOP Refer to the function truth table Begin Clock Suspend next cycle8 Exit Clock Suspend next cycle8. Maintain Clock Suspend.
Power-Down
All. Banks Idle7
Any State other than listed above
Abbreviations:
RA = Row Address CA = Column Address BS = Bank Select Address AP = Auto Precharge
Notes for SDRAM function truth table: 1. 2. 3. 4. 5. 6. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank. Must satisfy bus contention, bus turn around, and/or write recovery requirements. NOP to bank precharging or in Idle state. The precharge bank(s) indicated by BS and AP. Illegal if any bank is not Idle. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 8. Must be legal command as defined in the SDRAM function truth table.
V58C265164S Rev. 1.7 August 2001
30
Multibank Interleaving Read (CAS Latency = 2; Burst Length = 4)
T0 tRRD
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
V58C265164S Rev. 1.7 August 2001
CLK
MOSEL VITELIC
CLK High
Multibank Interleaving Read
CKE
CS
RAS
CAS
31
BAa Ra Ra Ra Rb Ca Rb Cb Rb BAb BAa BAb t RCDB t RCDA ACT A ACT B RD A RD B
WE
BA0, BA1
A11
A10, AP
A0-A9
DQS Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
DQ
DM
V58C265164S
Command
Read Interrupted by a Read (CAS Latency = 2; Burst Length = 8)
T0 tCCD
CLK CLK
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
T1
T2
T3
T4
T5
T6
T7
T8
Read Interrupted by a Read
CKE
CS RAS CAS WE BAa BAb
High
32
A11 Ca Cb DQS DQ DM RD A RD B Qa0 Qa1 Qb0 Qb1 Qb2 Qb3
BA0, BA1
A10, AP
A0-A9
Qb4
Qb5 Qb6
Qb7
V58C265164S
Command
T0 tRRD tRCD
CLK CLK CKE CS RAS CAS WE BAa Ra Rb BAb BAa High
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
Multi Bank Interleaving Write (@ BL = 4)
T1
T2
T3
T4
T5
T6
T7
T8
33
A11 Ra Rb Ca DQS DQ DM ACT A ACT B WR A Da0 t RCDB
BA BA0, BA1
BAb
A10, AP Cb
ADDR (A0~A9, A11)
Da1 Da2 Da3
Db0
Db1
Db2
Db3
V58C265164S
Command
WR B
T0 tRP
T1
T2
T3
T4
T5
T6
T7
T8
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
CK
CK High
CKE
CS
RAS
CAS
Auto Precharge After Read Burst (@ BL = 8, CL = 2)
34
Ba Ca Qa0 Qa1 Qa2 Qa3 Qa4 RAP
WE Ba Ra Ra Auto Precharge Start Ra
BA0, BA1
A11
A10, AP
A0-A9
DQS Qa5 Qa6 Qa7
DQ
DM BA
V58C265164S
Command
Auto Precharge After Write Burst (Burst Length = 8) T1 tRP T2 T3 T4 T5 T6 T7 T8 T9 T10
T0
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
CK
CK
CKE
High
CS
RAS
Auto Precharge After Write Burst (@ BL=8)
CAS
35
BAa Ca t WPST + t WR Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 WR
WE BAa Ra Ra Ra Auto Precharge Start
BA0, BA1
A11
A10, AP
A0-A9
DQS
DQ
DM BA
V58C265164S
Command
MOSEL VITELIC
Read Interrupted by Precharge (@BL = 8, CL = 2)
V58C265164S
T6
T7
T5
T4
Qa2
Qa3
Qa4
Qa5
T1
T2
T3
BAa
Ca
Qa0
Qa1
T0
High
DQS
CKE
V58C265164S Rev. 1.7 August 2001
36
Command
BA0, BA1
A11
A0-A9
RAS
CAS
WE
A10, AP
DM
DQ
CK
CK
CS
RD
PRE
BAa
Write Interrupted by a Read (CAS Latency = 2; Burst Length = 8) T1 tCDLR T2 T3 T4 T5 T6 T7 T8 T9 T10
T0
V58C265164S Rev. 1.7 August 2001
CK
MOSEL VITELIC
CK
CKE
High
CS
RAS
Write Interrupted by a Read (@BL=8, CL=2)
CAS
37
BAa BAb Ca Cb Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 WR RD
WE
BA0, BA1
A11
A10, AP
A0-A9
DQS Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
DQ
DM
V58C265164S
Command
Write Burst (Burst Length = 4)
Write Burst
T0 tWR
CLK CLK High
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
T1
T2
T3
T4
T5
T6
CKE CS
RAS
CAS WE BAa BAa
38
A11 Ca DQ DM WR Da0 Da1 Da2 Da3
BA0, BA1
A10, AP
A0-A9
DQS
V58C265164S
Command
PRE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
V58C265164S Rev. 1.7 August 2001
CLK
MOSEL VITELIC
CLK High
CKE
CS
RAS
Read Interrupted by a Write and Burst Stop
CAS
WE BAa BAb
39
Ca Cb Qa0 Qa1 RD BST LBST WR
BA (BA0, BA1)
A11
A10, AP
ADDR (A0-A9, A11)
DQS t DQSS Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
DQ
DM
V58C265164S
Command
Data Mask Function During Burst Write Cycles (CAS Latency = 2; Burst Length = 8) T1 T2 T3 T4 T5 T6
T0
CK
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
CK
CKE
High
CS
RAS
Data Mask Function (@BL=8) Only for Write
CAS
WE BAa
40
Ca Da0 Da1 Da2 Da3 Da4 Da5 WR
BA0, BA1
A11
A10, AP
A0-A9
DQS Da6 Da7
DQ
DM
V58C265164S
Command
Power Up Sequence and Auto Refresh (CBR) T0 200 clock min tRC T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
V58C265164S Rev. 1.7 August 2001
High level is required Minimum of two refresh cycles is required Two clock minimum Hi-Z ---DLL enable ---DLL reset ---Precharge all ---Mode register set ---Any command Hi-Z
MOSEL VITELIC
CLK
CLK
CKE
CS
RAS
CAS
WE
Power up Sequence and Auto Refresh (CBR)
BA0
41
BA1
A0
A1-A6
A7
A8
A9, A11
A10
DQ
DM
DQS
200 s min
V58C265164S
Precharge all
Mode Register Set Extended Mode Register Set
T0 tCK tRP T1 T2 T3 T4 T5 T6 T7
V58C265164S Rev. 1.7 August 2001
MOSEL VITELIC
CLK
CLK High Two clock minimum
CKE
CS
Mode Register/Extended Mode Register Set
RAS
CAS
42
---Precharge command all banks ADRSKEY Hi-Z ---Mode register set command ---Extended mode register set command ---Any command Hi-Z
WE
BA0, BA1
A9, A11
A10
A0-A8
DQ
DM
V58C265164S
DQS
MOSEL VITELIC
Package Diagram 66-Pin TSOP-II (400 mil)
V58C265164S
Units : Millimeters
(0.80) (0.50) (10*) (10*) 0.125 +0.075 -0.035 (0.50) 0 ~8
(R 0. 25 )
) (R 0. 2 5
#66
#34
10.16 0.10
(1.50)
#1 (1.50)
#33
0.665 0.05
0.210 0.05
(0.80)
(R 0. 15 )
0.05 MIN
(0.71)
0.65TYP 0.65 0.08
0.30 0.08 (10*)
0.10 MAX
( 4*
(R 0.1 5
(10*)
)
1.20MAX
22.22 0.10
0.25TYP
[
0.075 MAX
]
NOTE 1. ( ) IS REFERENCE
V58C265164S Rev. 1.7 August 2001
43
0.45~0.75
1.00 0.10
)
11.76 0.20
(10.76)
MOSEL VITELIC
U.S.A.
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WORLDWIDE OFFICES
TAIWAN
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V58C265164S
UK & IRELAND
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BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
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(c) Copyright 2000, MOSEL VITELIC Inc.
8/001 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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